A new low-power (LP) scan-based built-in self test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains. During the deterministic BIST phase, the design-for-testability architecture is modified slightly while short. Built in Self-Test (BIST) is a design technique that allows a circuit to test itself .The proposed method of a built-in self-test (BIST) design for fault detection and fault diagnosis of static-RAM (SRAM)-based field-programmable gate arrays (FPGAs). can test both the interconnect resources [wire channels and programmable switches (PSs)] and lookup tables (LUTs) in the configurable logic blocks (CLBs).The test pattern generator and output response analyzer are configured by CLBs in FPGAs. The target fault detection/diagnosis of the proposed BIST structure are open/short and delay faults in the wire channels, stuck on/off faults in PSs, andstuck-at-0/1 faults in LUTs. The testing process is performed by configuring the Test Pattern Generator (TPG), Output Response Analyzer (ORA) and Block under Test (BUT) in each test block.
low-power, fault detection and fault diagnosis, field-programmable gate arrays
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