Because of the increased complexity of designs in recent years, we now have multiple components on a single chip that employ independent clocks, meaning that these clocks are not synchronized. As a result, problems with Clock Domain Crossing will occur, which, if not resolved, will proliferate and destroy the entire chip. Data crossing clock domains can cause a variety of problems, including as metastability and data loss, which can lead to the device failing completely. To overcome the clock domain crossing concerns, this work presents a dual flip flop synchronizer that employs TSPC logic and is based on the SOI technology. TSPC synchronizer when implemented in SOI technology gives outstanding results. It improves the rise time by 46.15 %, the fall time by 28.57 %, dissipates 24.23% less power, power delay product by a huge margin of 59.20 % when compared to its bulk CMOS counterpart. When implemented on a chip, it also takes up the least amount of space. All the circuits are designed in DSCH and simulated in Microwind software.
TSPC, CDC, SOI, Synchronizer, Low Power
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