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Design of Low Power Dynamic Comparator using Reversible Logic

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Design of Low Power Dynamic Comparator using Reversible Logic


Mounica. E | Saranya. B | Shanmika. K | Balakumaran. D



Mounica. E | Saranya. B | Shanmika. K | Balakumaran. D "Design of Low Power Dynamic Comparator using Reversible Logic" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-4 | Issue-5, August 2020, pp.974-978, URL: https://www.ijtsrd.com/papers/ijtsrd32972.pdf

The Performance of circuits based in CMOS transistor logic is close to reaching its limit. A new efficient system or technology is needed to provide solutions to computing and integration issue. The proposed work addresses the above circumstance by implementing the reversible logic in dynamic comparator so that the number of transistors can be reduced. This logic can also be implemented in order to lower the power consumption and improve performance of circuit. The inputs and outputs of reversible logic gates can be uniquely retrievable from each other. The proposed reversible ripple carry adder is designed using L and M gates which requires only 18 transistors while the number of transistor implemented in CMOS implementation is 20. The critical path is made minimal so that the routing is reduced which makes the delays negligible. Reversible computing has its applications in computer security and transaction processing and also in those areas which require high energy efficiency, speed and performance.

Comparator, Delay effects, Reversible Logic gates, High performance computing, Logic circuits, Power dissipation


IJTSRD32972
Volume-4 | Issue-5, August 2020
974-978
IJTSRD | www.ijtsrd.com | E-ISSN 2456-6470
Copyright © 2019 by author(s) and International Journal of Trend in Scientific Research and Development Journal. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0) (http://creativecommons.org/licenses/by/4.0)

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