Implementation of 32-Bit RISC Processor using Reversible Gates

Mahesh Kumar Sharma; Jyoti Choudhary

Title:
Implementation of 32-Bit RISC Processor using Reversible Gates

Authors:
Jyoti Choudhary | Mahesh Kumar Sharma

Cite This Article :

Jyoti Choudhary | Mahesh Kumar Sharma "Implementation of 32-Bit RISC Processor using Reversible Gates" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-5, August 2019, pp.1789-1793, URL: https://www.ijtsrd.com/papers/ijtsrd26709.pdf

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Abstract :
Reversible logic is one of the emerging technologies having promising applications in quantum computing. The aim of this project is to design the schematic and simulation for a 32-bit RISC processor using reversible logic peres gate. Beside the functional development, by optimizing the speed of our processor in every block which is inside that, and to minimize the overall delay conventional gates are replaced with reversible gates. This reversible gates which are applicable in Nano technology, Quantum computing, Low power CMOS, Optical computing. This RISC embodies 15 basic instructions involving Arithmetic, Logical, Data Transfer and control instructions. To implement these instructions the design incorporates various design blocks like Control Unit (CU), Arithmetic and Logic Unit (ALU), Accumulator, Program Counter (PC), Instruction Register (IR), Memory and additional logic. Design is implemented and verified in VHDL in Xilinx 14.3.

Keywords :
RISC, Arithmetic Logic Unit, CISC, Reversible Gates

Publication Details:

Unique Identification Number : IJTSRD26709

Published In : Volume-3 | Issue-5, August 2019

Page Number(s) : 1789-1793

Publisher Name : IJTSRD | www.ijtsrd.com | E-ISSN 2456-6470

Copyright © 2019 by author(s) and International Journal of Trend in Scientific Research and Development Journal. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0) (http://creativecommons.org/licenses/by/4.0)

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