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FPGA Based Hybrid LMS Algorithm Design on Distributed Arithmetic

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FPGA Based Hybrid LMS Algorithm Design on Distributed Arithmetic

Yamuna P | B K Venu Gopal


Yamuna P | B K Venu Gopal "FPGA Based Hybrid LMS Algorithm Design on Distributed Arithmetic" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-1, December 2018, pp.558-563, URL: https://www.ijtsrd.com/papers/ijtsrd19018.pdf

Filter plays a major role for removal of unwanted signal/noise from the original signal, especially Adaptive FIR filter is easy to attract for many applications, where it is need to minimize computational requirement. This paper shows a novel pipelined design for low-power, high-throughput, and low-area implementation of adaptive ?lter based on distributed arithmetic (DA). The DA formulation utilized for two separate blocks weight update block and filtering operations requires larger area and is n’t suited for higher order filters therefore causes reduction in the throughput. These issues have been overcome by efficient distributed formulation of Adaptive filters. LMS adaptation performed on a sample by sample basis is replaced by a dynamic LUT update by the weight update scheme. Adder based shift accumulation for inner product computation replaced by conditional signed carry-save accumulation to reduces the sampling period and area density.

Distributed Arithmetic, LMS Adaptive Filter, VHDL, DA, Adaptive Filter, LMS algorithm, Carrysave adder, Noise Cancellation, Digital Signal Processing

Volume-3 | Issue-1, December 2018
IJTSRD | www.ijtsrd.com | E-ISSN 2456-6470
Copyright © 2019 by author(s) and International Journal of Trend in Scientific Research and Development Journal. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0) (http://creativecommons.org/licenses/by/4.0)

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