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Synthesis of 64-Bit Triple Data Encryption Standard Algorithm using VHDL

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Synthesis of 64-Bit Triple Data Encryption Standard Algorithm using VHDL

Simran | Parminder Singh Jassal


Simran | Parminder Singh Jassal "Synthesis of 64-Bit Triple Data Encryption Standard Algorithm using VHDL" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4, June 2018, pp.775-778, URL: https://www.ijtsrd.com/papers/ijtsrd14159.pdf

Data security is the most important requirement of today’s world, to transmit digital data from one place to another. We need to secure the transmitted data at the transmitting end so that no unauthorized user can access it. To encrypt the data at the transmitting point and decrypt the data at the receiving point we need the communication security[8] . Only the authorized user can get back the original text, provided they have the secret key. Cryptography is a technique to transmit protected data between two points. The word ‘Cryptography’ was invented by combining two Greek words, ‘Krypto’ meaning hidden and ‘graphene’ meaning writing. Cryptography is the study of mathematical techniques related to aspects of various information data security. It deals with protection of data on unsecured channel by altering the data in encrypt (coded)form. Basically, we have two cryptography techniques for digital data transfer, depending on how the encryption-decryption is carried out in the system, Symmetric Cryptography and Asymmetric Cryptography. DES, TRIPLE-DES, IDEA, AND BLOWFISH algorithms use symmetric cryptography technique. Due to the importance of the DES/TDES algorithm and the numerous applications that it has, our main concern DES/TDES Encryption/ Decryption using three keys and synthesize TDES, which give higher operating frequency. In this paper we present, TDES synthesis in VHDL, in Electronic Code Block(ECB) mode, of this commonly used cryptography scheme with aim to improve performance. The design is simulated and synthesized in Xilinx ISE 14.7 with family Virtex-7 (XC7VX330t– 3ffg1157). Our design achieves a operating frequency of 114.33 MHZ.

Cryptography, DES, TDES, Encryption, Decryption, Implementation Results

Volume-2 | Issue-4, June 2018
IJTSRD | www.ijtsrd.com | E-ISSN 2456-6470
Copyright © 2019 by author(s) and International Journal of Trend in Scientific Research and Development Journal. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0) (http://creativecommons.org/licenses/by/4.0)

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