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Alternative RAM Mapping Algorithm for Embedded Memory Blocks in FPGA

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Alternative RAM Mapping Algorithm for Embedded Memory Blocks in FPGA


Bhagyashree Ashok Gavhane | Prashant Vitthalrao Kathole

https://doi.org/10.31142/ijtsrd7172



Bhagyashree Ashok Gavhane | Prashant Vitthalrao Kathole "Alternative RAM Mapping Algorithm for Embedded Memory Blocks in FPGA" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-3, April 2018, pp.2542-2549, URL: https://www.ijtsrd.com/papers/ijtsrd7172.pdf

Contemporary ?eld-programmable gate array (FPGA) design requires a spectrum of available physical resources. As FPGA logic capacity has grown, locally accessed FPGA embedded memory blocks have increased in importance. When targeting FPGAs, application designers often specify high-level memory functions, which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this paper, a set of power efficient logical-to-physical RAM mapping algorithms is described, which converts user de?ned memory speci?cations to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-ef?cient choice. Our automated approach has been validated with both simulation of power dissipation and measurements of power dissipation on FPGA hardware. A comparison of measured power reductions to values determined via simulation con?rms the accuracy of our simulation approach. Our power-aware RAM mapping algorithms have been integrated into a commercial FPGA compiler and tested with 34 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 26% and overall core dynamic power can be reduced by 6% with a minimal loss (1%) in design performance. In addition, it is shown that the availability of multiple embedded memory block sizes in an FPGA reduces embedded memory dynamic power by an additional 9.6% by giving more choices to the computer-aided design algorithms.

Design automation, ?eld-programmable gate arrays (FPGAs), memory architecture, power demand


IJTSRD7172
Volume-2 | Issue-3, April 2018
2542-2549
IJTSRD | www.ijtsrd.com | E-ISSN 2456-6470
Copyright © 2019 by author(s) and International Journal of Trend in Scientific Research and Development Journal. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0) (http://creativecommons.org/licenses/by/4.0)

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