Shrinking process technology has the advantage of lower area of Integrated Circuits (I.C s). This has allowed adding more hardware (features) to existing circuits and enhancing the existing features, Example: - adding more cores to a micro-processor or increasing the resolution of the Video processing hardware of a mobile phone, etc. Execution of complex algorithms need more local memories (SRAMs) embedded in the hardware. As memories are densely packed structures compared to logic (gates and flip flops) the probability of fault occurrence in memories is higher. Thus, adding more complex logic has increased the probability of fault occurrence in ICs and thus decreasing the yield. In this paper we present a Reconfigurable Built in Self Repair (Re-BISR) technique to repair the faults in embedded memories. We also employ Error Correction Codes (ECC) to repair single bit faults in memories. Both the above techniques combined allow us to repair the faults and thereby increasing the yield and reliability of an IC. Re-BISR can repair the faults of several memories in an IC and thus has lesser hardware overhead compared to a dedicated BISR scheme where each RAM has a dedicated BISR module. However, Re-BISR is considerably slower compared to dedicate BISR as RE-BISR operates serially on each memory. Future version of Re-BISR contains a programmable MBIST scheme to accommodate several March algorithms and also include virtual blocks for redundant memories to increase the repair rate. We implement the project using Xilinx ISE tool for simulation and synthesis and the code is written in Verilog HDL.
Built-in redundancy analysis (BIRA), built-in self-repair (BISR), built-in self-test (BIST), yield, Re-BISR, Error correcting codes.
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