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A Performance Degradation Tolerance Way Tagged Cache

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A Performance Degradation Tolerance Way Tagged Cache

Karkagari Anjali | G. Kumara Swamy | M. Preethi


Karkagari Anjali | G. Kumara Swamy | M. Preethi "A Performance Degradation Tolerance Way Tagged Cache" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-5, August 2018, pp.1-5, URL: https://www.ijtsrd.com/papers/ijtsrd15729.pdf

For an electronic product or chip if functional faults exist, then the product or chip is of no use. Therefore, if we take a cache memory, a secondary memory for high-speed retrieval of data stored where functional faults exist. These functional faults in the data stored in the cache can be converted into performance faults so that the caches can still be marketable. In processors, caches are designed as Level 1(L1), Level 2(L2), and the least hard disk. If the processor wants the data from/to memory it checks the availability of data in upper-level cache L1 and if the data is found it sends to the processor. If the data is not found in L1, it checks in lower level cache L2 and next in L3 and at the least in slow memory or hard disk. So, in this process, many functional faults may exist which leads to making the processor faulty. So, to protect the cache memory ECC and BIST are used. For a cache redesign, a PDT cache is used where functional faults are converted into performance faults. We propose a new PDT way tagged cache design which leads to increased performance. This reduces fault rate with small hardware overhead by applying BIST or ECC method.

Cache memory, PDT, Memory Hierarchy, BIST, fault

Volume-2 | Issue-5, August 2018
IJTSRD | www.ijtsrd.com | E-ISSN 2456-6470
Copyright © 2019 by author(s) and International Journal of Trend in Scientific Research and Development Journal. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0) (http://creativecommons.org/licenses/by/4.0)

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