In this paper various flip-flop structures have been studied. In all designs to reduce power consumption, the Pulse Generator circuitry should be in build along with the flip-flop itself. If a pulse generator is included along with DPSCRFF structure, power consumption can be reduced. In this work a new design of flip-flop, Double Pulse Latch Flip-flop (DPLFF) is proposed. DPLFF eliminates unnecessary glitches, which consume more power. DPLFF consume less power for same delay as compared with other existing techniques, which is performing one of the fastest known flip-flops. In serial operation as shift register the proposed DPLFF can perform better at the higher frequency. The stacking of transistor in the latch stage cause reduction in subthreshold leakage current & thus the static power consumption is also less for DPLFF. This is better suited for low power circuits at deep submicron technology where leakages are more dominant.
DPLFF, Delay, Power Consumption, Speed, Latch, Flip-flop, Pulse Generator
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