Low Power Mix Logic Design Using Line Decoder A Review
In todays world, as the technology is developing so rapidly the designing of the systems are becoming more and more compact. In some systems even if the circuits are not compact still there is a need of less power consumption. This brief introduces a mixed logic design method for line decoders, combining transmission gate logic, pass transistor dual value logic, and static complementary metal oxide semiconductor CMOS . Two novel topologies are presented for the 2–4 decoder a 14 transistor topology aiming on minimizing transistor count and power dissipation and a 15 transistor topology aiming on high power delay performance. Both normal and inverting decoders are implemented in each case, yielding a total of four new designs. Additionally, four new 4–16 decoders are designed by using mixed logic 2–4 predecoders combined with standard CMOS postdecoder. Low Power is a well established discipline it has undergone lot of developments from transistor sizing, process shrinkage, voltage scaling, clock gating, etc., to adiabatic logic. This paper aims to elaborate on the recent trends in the low power design. This paper is the review of use of line decoder to reduce power consumption as well as reduce number of transistor and power dissipation. 1. INTRODUCTION In the modern age, there is an immense need of applications which consume less power and are small in area. The low power design is major issue in high performance digital system, such as microprocessors, digital signal processors DSPs and other applications. Designing of low power VLSI circuits is a technological need in these due to the high demand for portable consumer electronics products.
2 to 4 line decoder, CMOS, Transmission Gate, Pass Transistor logic
Ku. Priyanka M. Raut | Dr. R. M. Deshmukh